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FEATURES
n n n n n n n n n
LT3825 Isolated No-Opto Synchronous Flyback Controller with Wide Input Supply Range DESCRIPTION
The LT(R)3825 is an isolated switching regulator controller designed for medium power flyback topologies. A typical application is 10W to 60W with input voltage limited only by external power path components. A third transformer winding provides output voltage feedback. The LT3825 is a current mode controller that regulates output voltage based on sensing secondary voltage via a transformer winding during flyback. This allows for tight output regulation without the use of an optoisolator, improving dynamic response and reliability. Synchronous rectification increases converter efficiency and improves output cross regulation in multiple output converters. The LT3825 operates in forced continuous conduction mode which improves cross regulation in multiple winding applications. Switching frequency is user programmable and can be externally synchronized. The part also has load compensation, undervoltage lockout and soft-start circuity.
L, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6948466, 5841643.
Senses Output Voltage Directly from Primary Side Winding--No Optoisolator Required Synchronous Driver for High Efficiency Input Voltage Limited Only by External Power Components Accurate Output Regulation Without User Trims Switching Frequency from 50kHz to 250kHz Synchronizable Load Compensation Programmable Undervoltage Lockout Available in a Thermally Enhanced 16-Lead TSSOP Package
APPLICATIONS
n n n n
Isolated Medium Power (10W to 60W) Supplies Isolated Telecom, Medical Converters Instrumentation Power Supplies Isolated Power over Ethernet Supplies
TYPICAL APPLICATION
EFFICIENCY (%)
Efficiency
92 90 36VIN 88 48VIN 72VIN
48V to 3.3V at 12V Isolated Supply
VIN+ 36V TO 72V 100pF 28.7k T1 3.01k 402k 2.2F UVLO 15k LT3825 PGDLY tON SYNC RCMP ENDLY 12k 100k 2.1k 150k 47pF SENSE- VC OSC GND SFST CCMP 10nF 0.22F 0.1F 100k
3825 TA01a
86 84 82 80 78 2 3 4
*
T1
470F x4
VOUT+ 3.3V 12A
*
20
47k
20
*
47 56789 LOAD CURRENT (A) 10 11 12
3825 TA01b
+
47F FB VCC SG SG PG SENSE+ x2 SG 0.02 330 0.1F
Regulation
3.43 1F 15 2.2nF 3.38 3.33 OUTPUT (V) 3.28 3.23 3.18 3.13 2 3 4 56789 LOAD CURRENT (A) 36VIN 48VIN 72VIN
*
*
10k
10 11 12
3825 TA01c
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LT3825 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW SG VCC tON ENDLY SYNC SFST OSC FB 1 2 3 4 5 6 7 8 17 16 PG 15 PGDLY 14 RCMP 13 CCMP 12 SENSE+ 11 SENSE- 10 UVLO 9 VC
VCC to GND Low Impedance Source ........................ -0.3V to 18V Current Fed (VCC has Internal 19.5V Clamp) ...........30mA into VCC UVLO, SYNC Pin Voltage ........................... -0.3V to VCC SENSE-, SENSE+ Pin Voltage ...................... -0.5V, +0.5V FB Pin Current........................................................2mA VC Pin Current....................................................... 1mA Operating Junction Temperature Range (Notes 2, 3) .......................................... -40C to 125C Storage Temperature Range.................. -65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C
FE PACKAGE 16-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 40C/W, JC = 10C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LT3825EFE#PBF LEAD BASED FINISH LT3825EFE TAPE AND REEL LT3825EFE#TRPBF TAPE AND REEL LT3825EFE#TR PART MARKING 3825EFE PART MARKING 3825EFE PACKAGE DESCRIPTION 16-Lead Plastic 4.4mm TSSOP PACKAGE DESCRIPTION 16-Lead Plastic 4.4mm TSSOP TEMPERATURE RANGE -40C to 125C TEMPERATURE RANGE -40C to 125C
Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 14V; PG, SG Open; VC = 1.5V, VSENSE- = 0V; RCMP = 1k, RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
PARAMETER Power Supply VCC Turn-On Voltage VCC Turn-Off Voltage VCC Hysteresis VCC Shunt Clamp VCC Supply Current (Note 5) (ICC) VCC Start-Up Current Feedback Amplifier Feedback Regulation Voltage (VFB) Feedback Pin Input Bias Current Feedback Amplifier Transconductance Feedback Amplifier Source or Sink Current Feedback Amplifier Clamp Voltage VFB = 0.9V VFB = 1.4V RCMP Open IC = 10A
l
CONDITIONS
MIN 14.0 8 4.0 19.5 4
TYP 15.3 9.7 5.6 20.5 6.4 180
MAX 16.0 11 6.5 10 400 1.251 1400 90
UNITS V V V V mA A V nA mho A V
VCC(ON) - VCC(OFF) VUVLO = 0V, IVCC = 15mA VC = Open VCC = 10V
1.220 700 25
1.237 200 1000 55 2.56
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LT3825 ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 14V; PG, SG Open; VC = 1.5V, VSENSE- = 0V; RCMP = 1k, RtON = 90k, RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
PARAMETER Reference Voltage Line Regulation Feedback Amplifier Voltage Gain Soft-Start Charging Current Soft-Start Discharge Current Control Pin Threshold (VC) Gate Outputs PG, SG Output High Level PG, SG Output Low Level PG, SG Output Shutdown Strength PG Rise Time SG Rise Time PG, SG Fall Time Current Amplifier Switch Current Limit at Maximum VC VSENSE/VC Sense Voltage Overcurrent Fault Voltage Timing Switching Frequency (fOSC) Oscillator Capacitor Value (COSC) Minimum Switch On Time (tON(MIN)) Flyback Enable Delay Time (tED) PG Turn-On Delay Time (tPGDLY) Maximum Switch Duty Cycle SYNC Pin Threshold SYNC Pin Input Resistance Load Compensation Load Comp to VSENSE Offset Voltage Feedback Pin Load Compensation Current UVLO Function UVLO Pin Threshold (VUVLO) UVLO Pin Bias Current VUVLO = 1.2V VUVLO = 1.3V

CONDITIONS 12V VCC 18V VC = 1.2V to 1.7V VSFST = 1.5V VSFST = 1.5V, VUVLO = 0V Duty Cycle = Min
MIN
TYP 0.005 1400
MAX 0.02 25
UNITS %/V V/V A mA V
16 0.8
20 1.3 1.0
6.6
7.4 0.01 1.6 11 15 10
8.0 0.05 2.3
V V V ns ns ns
VUVLO = 0V; IPG, ISG = 20mA CPG = 1nF CSG = 1nF CPG, CSG = 1nF VSENSE+ VSENSE+, VSFST < 1V COSC = 100pF (Note 6)
88
98 0.07 206
110 230 110 200
mV V/V mV kHz pF ns ns ns %
84 33
100 200 265 200
85
88 1.53 40 2.1
V k mV A
VRCMP with VSENSE+ = 0V VSENSE+ = 20mV, VFB = 1.230V 1.215 -0.25 -4.50
1 20 1.240 0 -3.4 1.265 0.25 -2.50
V A A
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: The LT3825E is guaranteed to meet performance specifications from 0C to 125C. Specifications over the -40C to 125C operating
temperature range are assured by design, characterization and correlation with statistical process controls. Note 4: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD * 40C/W) Note 5: Supply current does not include gate charge current to the MOSFETs. See Applications Information. Note 6: Component value range guaranteed by design.
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LT3825 TYPICAL PERFORMANCE CHARACTERISTICS
VCC(0N) and VCC(OFF) vs Temperature
16 15 14 IVCC (mA) IVCC (A) 13 VCC (V) 12 11 VCC(OFF) 10 9 8 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 50 0 -50 -25 200 150 100 VCC(ON) 300 250
VCC Start-Up Current vs Temperature
10 9 8 7 6
VCC Current vs Temperature
DYNAMIC CURRENT CPG = 1nF, CSG = 1nF, fOSC = 100kHz
STATIC PART CURRENT 5 4 VCC = 14V 3 50 -50 -25 25 75 0 TEMPERATURE (C)
50 25 75 0 TEMPERATURE (C)
100
125
100
125
3825 G01
3825 G02
3825 G03
SENSE Voltage vs Temperature
110 108 106 SENSE VOLTAGE (mV) 104 102 100 98 96 94 92 90 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 FB = 1.1V SENSE = VSENSE+ WITH VSENSE- = 0V SENSE VOLTAGE (mV) 220
SENSE Fault Voltage vs Temperature
SENSE = VSENSE+ - 215 WITH VSENSE = 0V 210 fOSC (kHz) 205 200 195 190 185 180 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 110 108 106 104 102 100 98 96 94 92
Oscillator Frequency vs Temperature
COSC = 100pF
90 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
3825 G04
3825 G05
3825 G06
VFB vs Temperature
1.240 1.239 1.238 1.237 VFB (V) 1.236 1.235 1.234 1.233 1.232 1.231 1.230 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 FEEDBACK PIN INPUT BIAS (nA) 250 200 150 100 50 300
Feedback Pin Input Bias vs Temperature
1.04 RCMP OPEN 1.03 1.02 VFB RESET (V) 1.01 1.00 0.99 0.98 0.97 50 25 75 0 TEMPERATURE (C) 100 125
VFB Reset vs Temperature
0 -50 -25
0.96 -50 -25
0
50 75 25 TEMPERATURE (C)
100
125
3825 G07
3825 G08
3825 G09
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LT3825 TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Amplifier Output Current vs VFB
70 125C 50 30 IVC (A) 10 -10 -30 -50 -70 0.9 1 1.1 1.2 VFB (V) 1.3 1.4 1.5
3825 G10
Feedback Amplifier Source and Sink Current vs Temperature
70 25C -40C 60 IVC (A) 55 50 950 45 40 -50 65 SOURCE CURRENT VFB = 1.1V SINK CURRENT VFB = 1.4V 1100
Feedback Amplifier gm vs Temperature
1050 gm (mho)
1000
-25
50 25 75 0 TEMPERATURE (C)
100
125
900 -50
-25
75 0 25 50 TEMPERATURE (C)
100
125
3825 G11
3825 G12
Feedback Amplifier Voltage Gain vs Temperature
1700 1650 1600 1550 1500 UVLO (V) AV (V/V) 1450 1400 1350 1300 1250 1200 1150 1100 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 1.225 1.240 1.245 1.250
UVLO vs Temperature
3.7 3.6 3.5 IUVLO (A) 3.4 3.3 3.2 3.1
IUVLO Hysteresis vs Temperature
1.235
1.230
1.220 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3.0 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
3825 G13
3825 G14
3825 G15
Soft-Start Charge Current vs Temperature
23 22 SFST CHARGE CURRENT (A) 21 TIME (ns) 20 19 18 17 16 15 -50 -25 0 75 50 25 TEMPERATURE (C) 100 125 80 70 60 50
PG, SG Rise and Fall Times vs Load Capacitance
TA = 25C 21.5
VCC Clamp Voltage vs Temperature
ICC = 10mA
21.0
40 30 RISE TIME 20 10 0 0 1 2 34567 CAPACITANCE (nF) 8 9 10
VCC (V)
FALL TIME
20.5
20.0
19.5
19.0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
3825 G16
3825 G17
3825 G18
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LT3825 TYPICAL PERFORMANCE CHARACTERISTICS
Minimum PG On Time vs Temperature
340 330 320 tON(MIN) (ns) tPGDLY (ns) 310 300 290 280 270 260 -50 -25 0 75 50 25 TEMPERATURE (C) 100 125 50 0 -50 160 140 -50 -25 200 tED (ns) 150 100 RPGDLY = 16.9k RtON(MIN) = 158k 300 250 RPGDLY = 27.4k 220 200 180
PG Delay Time vs Temperature
260 240
Enable Delay Time vs Temperature
RENDLY = 90k
-25
25 0 75 50 TEMPERATURE (C)
100
125
50 25 75 0 TEMPERATURE (C)
100
125
3825 G19
3825 G20
3825 G21
PIN FUNCTIONS
SG (Pin 1): Synchronous Gate Drive Output. This pin provides an output signal for a secondary-side synchronous switch. Large dynamic currents may flow during voltage transitions. See the Applications Information for details. VCC (Pin 2): Supply Voltage Pin. Bypass this pin to ground with a 4.7F capacitor or more. This pin has a 19.5V clamp to ground. VCC has an undervoltage lockout function that turns the part on when VCC is approximately 15.3V and off at 9.7V. In a conventional "trickle-charge" bootstrapped configuration, the VCC supply current increases significantly during turn-on causing a benign relaxation oscillation action on the VCC pin if the part does not start normally. tON (Pin 3): Pin for external programming resistor to set the minimum time that the primary switch is on for each cycle. Minimum turn-on facilitates the isolated feedback method. See Applications Information for details. ENDLY (Pin 4): Pin for external programming resistor to set enable delay time. The enable delay time disables the feedback amplifier for a fixed time after the turn-off of the primary-side MOSFET. This allows the leakage inductance voltage spike to be ignored for flyback voltage sensing. See Applications Information for details. SYNC (Pin 5): Pin for synchronizing the internal oscillator with an external clock. The positive edge on a pulse causes the oscillator to discharge causing PG to go low (off) and SG high (on). The sync threshold is typically 1.6V. See Applications Information for details. Tie to ground if unused. SFST (Pin 6): This pin, in conjunction with a capacitor to ground, controls the ramp-up of peak primary current as sensed through the sense resistor. This is used to control converter inrush current at start-up. The VC pin voltage cannot exceed the SFST pin voltage, so as SFST increases, the maximum voltage on VC increases commensurately, allowing higher peak currents. Total VC ramp time is approximately 70ms per F of capacitance. Leave pin open if not using the soft-start function. OSC (Pin 7): This pin in conjunction with an external capacitor defines the controller oscillator frequency. The frequency is approximately 100kHz * 100/COSC(pF). FB (Pin 8): Pin for the feedback node for the power supply feedback amplifier. Feedback is usually sensed via a third winding and enabled during the flyback period. This pin also sinks additional current to compensate for load current variation as set by the RCMP pin. Keep the Thevenin equivalent resistance of the feedback divider at roughly 3k.
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LT3825 PIN FUNCTIONS
VC (Pin 9): Pin used for frequency compensation for the switcher control loop. It is the output of the feedback amplifier and the input to the current comparator. Switcher frequency compensation components are normally placed on this pin to ground. The voltage on this pin is proportional to the peak primary switch current. The feedback amplifier output is enabled during the synchronous switch on time. UVLO (Pin 10): A resistive divider from VIN to this pin sets an undervoltage lockout based upon VIN level (not VCC). When the UVLO pin is below its threshold, the gate drives are disabled, but the part draws its normal quiescent current from VCC. The VCC undervoltage lockout supersedes this function so VCC must be great enough to start the part. The bias current on this pin has hysteresis such that the bias current is sourced when the UVLO threshold is exceeded. This introduces a hysteresis at the pin equivalent to the bias current change times the impedance of the upper divider resistor. The user can control the amount of hysteresis by adjusting the impedance of the divider. See the Applications Information for details. Tie the UVLO pin to VCC if you are not using this function. SENSE- (Pin 11), SENSE+ (Pin 12): These pins are used to measure primary side switch current through an external sense resistor. Peak primary side current is used in the converter control loop. Make Kelvin connections to the sense resistor to reduce noise problems. SENSE- connects to the ground side. At maximum current (VC at its maximum voltage) it has a 98mV threshold. The signal is blanked (ignored) during the minimum turn-on time. CCMP (Pin 13): Pin for external filter capacitor for the optional load compensation function. Load compensation reduces the effects of parasitic resistances in the feedback sensing path. A 0.1F ceramic capacitor suffices for most applications. Short this pin to GND in less demanding applications that don't require load compensation. RCMP (Pin 14): Pin for optional external load compensation resistor. Use of this pin allows for nominal compensation of parasitic resistances in the feedback sensing path. In less demanding applications, this resistor is not needed and this pin can be left open. See Applications Information for details. PGDLY (Pin 15): Pin for external programming resistor to set delay from synchronous gate turn-off to primary gate turn-on. See Applications Information for details. PG (Pin 16): Gate Drive Pin for the Primary Side MOSFET Switch. Large dynamic currents flow during voltage transitions. See the Applications Information for details. GND (Exposed Pad, Pin 17): This is the ground connection for both signal ground and gate driver grounds. This GND should be connected to the PCB ground plane. Careful attention must be paid to ground layout. See Applications Information for details.
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LT3825 BLOCK DIAGRAM
2 VCC VCC UVLO 19.5V 0.7 FB 1.3 8 CLAMPS
+ -
15.3V
+ -
- +
S R Q Q
ERROR AMP VC 9
1.235V REFERENCE (VFB)
3V INTERNAL REGULATOR
COLLAPSE DETECT
UVLO 10
IUVLO TSD
CURRENT TRIP SENSE+ RCMPF 50k SET ENABLE CCMP
SLOPE COMPENSATION 7 OSC OSCILLATOR
5 3 15 4
SYNC tON LOGIC BLOCK TO FB
+
-
LOAD COMPENSATION
PGDLY ENDLY
VCC PGATE SGATE GATE DRIVE PG 16
+ -
3V VCC GATE DRIVE SG GND 1 17
8
-
+
-
CURRENT COMPARATOR
+
+
-
UVLO
1V
OVERCURRENT FAULT SENSE- CURRENT SENSE AMP 11
+
SFST 6 12 13 RCMP 14
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-
+
LT3825 FLYBACK FEEDBACK AMPLIFIER
VFLBK FLYBACK R1 8 R2 FB 1V VFB 1.25V LT3825 FEEDBACK AMP T1
*
VC 9 CVC VIN PRIMARY
- + + -
*
SECONDARY COUT
*
COLLAPSE DETECT MP MS
ISOLATED OUTPUT
R ENABLE S Q
3825 FFA
TIMING DIAGRAM
PRIMARY SIDE MOSFET DRAIN VOLTAGE
VFLBK VIN
0.8 * VFLBK
PG VOLTAGE
SG VOLTAGE
3825 TD
tON(MIN) ENABLE DELAY
MIN ENABLE FEEDBACK AMPLIFIER ENABLED
PG DELAY
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LT3825 OPERATION
The LT3825 is a current mode switcher controller IC designed specifically for use in an isolated flyback topology employing synchronous rectification. The LT3825 operation is similar to traditional current mode switchers. The major difference is that output voltage feedback is derived via sensing the output voltage through the transformer. This precludes the need of an optoisolator in isolated designs greatly improving dynamic response and reliability. The LT3825 has a unique feedback amplifier that samples a transformer winding voltage during the flyback period and uses that voltage to control output voltage. The internal blocks are similar to many current mode controllers. The differences lie in the flyback feedback amplifier and load compensation circuitry. The logic block also contains circuitry to control the special dynamic requirements of flyback control. For more information on the basics of current mode switcher/controllers and isolated flyback converters see Application Note 19. Feedback Amplifier--Pseudo DC Theory For the following discussion refer to the simplified Flyback Feedback Amplifier diagram. When the primary side MOSFET switch MP turns off, its drain voltage rises above the VIN rail. Flyback occurs when the primary MOSFET is off and the synchronous secondary MOSFET is on. During flyback the voltage on nondriven transformer pins is determined by the secondary voltage. The amplitude of this flyback pulse as seen on the third winding is given as: VFLBK = VOUT + ISEC * ESR + RDS(ON) NSF compares the voltage to the internal bandgap reference. The feedback amp is actually a transconductance amplifier whose output is connected to VC only during a period in the flyback time. An external capacitor on the VC pin integrates the net feedback amp current to provide the control voltage to set the current mode trip point. The regulation voltage at the FB pin is nearly equal to the bandgap reference VFB because of the high gain in the overall loop. The relationship between VFLBK and VFB is expressed as: VFLBK = R1+ R2 * VFB R2
Combining this with the previous VFLBK expression yields an expression for VOUT in terms of the internal reference, programming resistors and secondary resistances: VOUT = R1+ R2 * VFB * NSF - ISEC * ESR + RDS(ON) R2
(
)
The effect of nonzero secondary output impedance is discussed in further detail; see Load Compensation Theory. The practical aspects of applying this equation for VOUT are found in the Applications Information. Feedback Amplifier Dynamic Theory So far, this has been a pseudo-DC treatment of flyback feedback amplifier operation. But the flyback signal is a pulse, not a DC level. Provision must be made to enable the flyback amplifier only when the flyback pulse is present. This is accomplished by the "Enable" line in the diagram. Timing signals are then required to enable and disable the flyback amplifier. There are several timing signals which are required for proper LT3825 operation. Please refer to the Timing Diagram. Minimum Output Switch On Time (tON(MIN)) The LT3825 affects output voltage regulation via flyback pulse action. If the output switch is not turned on, there is no flyback pulse and output voltage information is not available. This causes irregular loop response and start-up/latch-up problems. The solution is to require the primary switch to be on for an absolute minimum time per each oscillator cycle. If the output load is less than
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(
)
RDS(ON) = on resistance of the synchronous MOSFET MS ISEC = transformer secondary current ESR = impedance of secondary circuit capacitor, winding and traces NSF = transformer effective secondary-to-feedback winding turns ratio (i.e., NS/NFLBK) The flyback voltage is scaled by an external resistive divider R1/R2 and presented at the FB pin. The feedback amplifier
10
LT3825 OPERATION
that developed under these conditions, forced continuous operation normally occurs. See Applications Information for further details. Enable Delay (ENDLY) The flyback pulse appears when the primary side switch shuts off. However, it takes a finite time until the transformer primary side voltage waveform represents the output voltage. This is partly due to rise time on the primary side MOSFET drain node but, more importantly, is due to transformer leakage inductance. The latter causes a voltage spike on the primary side, not directly related to output voltage. Some time is also required for internal settling of the feedback amplifier circuitry. In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. This is termed "enable delay." In certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. See Applications Information for further details. Collapse Detect Once the feedback amplifier is enabled, some mechanism is then required to disable it. This is accomplished by a collapse detect comparator, which compares the flyback voltage (FB referred) to a fixed reference, nominally 80% of VFB. When the flyback waveform drops below this level, the feedback amplifier is disabled. Minimum Enable Time The feedback amplifier, once enabled, stays enabled for a fixed minimum time period termed "minimum enable time." This prevents lockup, especially when the output voltage is abnormally low; e.g., during start-up. The minimum enable time period ensures that the VC node is able to "pump up" and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. This time is set internally. Effects of Variable Enable Period The feedback amplifier is enabled during only a portion of the cycle time. This can vary from the fixed minimum enable time described to a maximum of roughly the "off" switch time minus the enable delay time. Certain parameters of feedback amp behavior are directly affected by the variable enable period. These include effective transconductance and VC node slew rate. Load Compensation Theory The LT3825 uses the flyback pulse to obtain information about the isolated output voltage. An error source is caused by transformer secondary current flow through the synchronous MOSFET RDS(ON) and real life nonzero impedances of the transformer secondary and output capacitor. This was represented previously by the expression "ISEC * (ESR + RDS(ON))." However, it is generally more useful to convert this expression to effective output impedance. Because the secondary current only flows during the off portion of the duty cycle (DC), the effective output impedance equals the lumped secondary impedance divided by OFF time DC. Since the OFF time duty cycle is equal to 1 - DC then: RS(OUT) = where: RS(OUT) = effective supply output impedance DC = duty cycle RDS(ON) and ESR are as defined previously This impedance error may be judged acceptable in less critical applications, or if the output load current remains relatively constant. In these cases the external FB resistive divider is adjusted to compensate for nominal expected error. In more demanding applications, output impedance error is minimized by the use of the load compensation function. Figure 1 shows the Block Diagram of the load compensation function. Switch current is converted to a voltage by the external sense resistor, averaged and lowpass filtered by the internal 50k resistor RCMPF and the external capacitor on CCMP . This voltage is impressed across the external RCMP resistor by op amp A1 and transistor Q3 producing a current at the collector of Q3 that is subtracted from the
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ESR + RDS(ON) 1 - DC
11
LT3825 OPERATION
VFLBK T1
Average primary side current is expressed in terms of output current as follows: IIN = K1 * IOUT where:
*
R1
FB 8 Q1 Q2 VFB VIN
* *
R2
LOAD COMP I
MP
K1 =
+
Q3 A1
VOUT VIN * Eff
-
RCMPF + 50k SENSE 12
So the effective change in VOUT target is: VOUT = K1* IOUT * RSENSE * R1* NSF RCMP
14 RCMP
13 CCMP
RSENSE
3825 F01
Figure 1. Load Compensation Diagram
thus : R VOUT = K1* SENSE * R1* NSF IOUT RCMP where:
FB node. This effectively increases the voltage required at the top of the R1/R2 feedback divider to achieve equilibrium. The average primary side switch current increases to maintain output voltage regulation as output loading increases. The increase in average current increases the RCMP resistor current which affects a corresponding increase in sensed output voltage, compensating for the IR drops. Assuming a relatively fixed power supply efficiency, Eff, power balance gives: POUT = Eff * PIN VOUT * IOUT = Eff * VIN * IIN
K1 = dimensionless variable related to VIN, VOUT and efficiency as explained above RSENSE = external sense resistor Nominal output impedance cancellation is obtained by equating this expression with RS(OUT): K1 * ESR + RDS(ON) RSENSE * R1 * NSF = RCMP 1 - DC
Solving for RCMP gives: RCMP = K1 * RSENSE * (1 - DC) * R1 * NSF ESR + RDS(ON)
The practical aspects of applying this equation to determine an appropriate value for the RCMP resistor are found in the Applications Information.
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LT3825 APPLICATIONS INFORMATION
Transformer Design Transformer design/specification is the most critical part of a successful application of the LT3825. The following sections provide basic information about designing the transformer and potential tradeoffs. If you need help, the LTC Applications group is available to assist in the choice and/or design of the transformer. Turns Ratios The design of the transformer starts with determining duty cycle (DC). DC impacts the current and voltage stress on the power switches, input and output capacitor RMS currents and transformer utilization (size vs power). The ideal turns ratio is: NIDEAL = VOUT 1 - DC * VIN DC For a multiple output transformer, the turns ratio between output windings is critical and affects the accuracy of the voltages. The ratio between two output voltages is set with the formula VOUT2 = VOUT1 * N21 where N21 is the turns ratio between the two windings. Also keep the secondary MOSFET RDS(ON) small to improve cross regulation. The feedback winding usually provides both the feedback voltage and power for the LT3825. So set the turns ratio between the output and feedback winding to provide a rectified voltage that under worst-case conditions is greater than the 11V maximum VCC turn-off voltage. NSF > VOUT 11+ VF 1 5 = 11+ 0.7 2.34
For our example: NSF > 1 3 Leakage Inductance We will choose
Avoid extreme duty cycles as they, in general, increase current stresses. A reasonable target for duty cycle is 50% at nominal input voltage. For instance, if we wanted a 48V to 5V converter at 50% DC then: NIDEAL = 5 1 - 0.5 1 * = 48 0.5 9.6
Transformer leakage inductance (on either the primary or secondary) causes a spike after the primary side switch turn-off. This is increasingly prominent at higher load currents, where more stored energy is dissipated. Higher flyback voltage may break down the MOSFET switch if it has too low a BVDSS rating. One solution to reducing this spike is to use a snubber circuit to suppress the voltage excursion. However, suppressing the voltage extends the flyback pulse width. If the flyback pulse extends beyond the enable delay time, output voltage regulation is affected. The feedback system has a deliberately limited input range, roughly 50mV referred to the FB node. This rejects higher voltage leakage spikes because once a leakage spike is several volts in amplitude, a further increase in amplitude has little effect on the feedback system. Therefore, it is advisable to arrange the snubber circuit to clamp at as high a voltage as possible, observing MOSFET breakdown, such that leakage spike duration is as short as possible. Application Note 19 provides a good reference on snubber design.
In general, better performance is obtained with a lower turns ratio. A DC of 45.5% yields a 1:8 ratio. Note the use of the external feedback resistive divider ratio to set output voltage provides the user additional freedom in selecting a suitable transformer turns ratio. Turns ratios that are the simple ratios of small integers; e.g., 1:1, 2:1, 3:2 help facilitate transformer construction and improve performance. When building a supply with multiple outputs derived through a multiple winding transformer, lower duty cycle can improve cross regulation by keeping the synchronous rectifier on longer, and thus, keep secondary windings coupled longer.
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As a rough guide, leakage inductance of several percent (of mutual inductance) or less may require a snubber, but exhibit little to no regulation error due to leakage spike behavior. Inductances from several percent up to perhaps ten percent cause increasing regulation error. Avoid double digit percentage leakage inductances as there is a potential for abrupt loss of control at high load current. This curious condition potentially occurs when the leakage spike becomes such a large portion of the flyback waveform that the processing circuitry is fooled into thinking that the leakage spike itself is the real flyback signal! It then reverts to a potentially stable state whereby the top of the leakage spike is the control point, and the trailing edge of the leakage spike triggers the collapse detect circuitry. This typically reduces the output voltage abruptly to a fraction, roughly one-third to two-thirds of its correct value. Once load current is reduced sufficiently, the system snaps back to normal operation. When using transformers with considerable leakage inductance, exercise this worst-case check for potential bistability: 1. Operate the prototype supply at maximum expected load current. 2. Temporarily short circuit the output. 3. Observe that normal operation is restored. If the output voltage is found to hang up at an abnormally low value, the system has a problem. This is usually evident by simultaneously viewing the primary side MOSFET drain voltage to observe firsthand the leakage spike behavior. A final note--the susceptibility of the system to bistable behavior is somewhat a function of the load current/voltage characteristics. A load with resistive--i.e., I = V/R behavior--is the most apt to be bistable. Capacitive loads that exhibit I = V2/R behavior are less susceptible. Secondary Leakage Inductance Leakage inductance on the secondary forms an inductive divider on the transformer secondary, reducing the size of the feedback flyback pulse. This increases the output voltage target by a similar percentage. Note that unlike leakage spike behavior, this phenomenon is independent of load. Since the secondary leakage inductance is a constant percentage of mutual inductance (within manufacturing variations), the solution is to adjust the feedback resistive divider ratio to compensate. Winding Resistance Effects Primary or secondary winding resistance acts to reduce overall efficiency (POUT/PIN). Secondary winding resistance increases effective output impedance degrading load regulation. Load compensation can mitigate this to some extent but a good design keeps parasitic resistances low. Bifilar Winding A bifilar or similar winding is a good way to minimize troublesome leakage inductances. Bifilar windings also improve coupling coefficients and thus improve cross regulation in multiple winding transformers. However, tight coupling usually increases primary-to-secondary capacitance and limits the primary-to-secondary breakdown voltage, so it isn't always practical. Primary Inductance The transformer primary inductance, LP , is selected based on the peak-to-peak ripple current ratio (X) in the transformer relative to its maximum value. As a general rule, keep X in the range of 20% to 40% ripple current (i.e., X = 0.2 to 0.4). Higher values of ripple will increase conduction losses, while lower values will require larger cores.
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Ripple current and percentage ripple is largest at minimum duty cycle; in other words, at the highest input voltage. LP is calculated from: LP The main design goals for core selection are reducing copper losses and preventing saturation. Ferrite core material saturates hard, rapidly reducing inductance when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and, consequently, output voltage ripple. Do not allow the core to saturate! The maximum peak primary current occurs at minimum VIN:
IPK = now : DCMAX = 1+ 1 = N * VIN(MIN) VOUT 1 = 52.6% 1 36 1+ * 85 = PIN X * 1+ MIN VIN(MIN) * DCMAX 2
( VIN(MAX) * DCMIN )2 = ( VIN(MAX) * DCMIN )2 * Eff =
fOSC * XMAX * PIN fOSC * XMAX * POUT
where: fOSC is the oscillator frequency DCMIN is the DC at maximum input voltage XMAX is ripple current ratio at maximum input voltage For a 48V (VIN = 36V to 72V) to 5V/8A converter with 90% efficiency, POUT = 40W and PIN = 44.44W. Using X = 0.4 and fOSC = 200kHz: DCMIN = 1+ 1 = N * VIN(MAX) VOUT
2
1 = 35.7% 1 72 1+ * 85 = 186H
XMIN
( VIN(MIN) * DCMAX ) =
fOSC * LP * PIN = 0.202
2
(36 * 52.6%)
2
200kHz * 186H * 44.44
LP =
(72V * 0.357)
Using the example numbers leads to: IPK = 0.202 44.44W = 2.58A * 1+ 36 * 0.526 2
200kHz * 0.4 * 44.44W
Optimization might show that a more efficient solution is obtained at higher peak current but lower inductance and the associated winding series resistance. A simple spreadsheet program is useful for looking at tradeoffs. Transformer Core Selection Once LP is known, the type of transformer is selected. High efficiency converters use ferrite cores to minimize core loss. Actual core loss is independent of core size for a fixed inductance, but decreases as inductance increases. Since increased inductance is accomplished through more turns of wire, copper losses increase. Thus transformer design balances core and copper losses. Remember that increased winding resistance will degrade cross regulation and increase the amount of load compensation required.
Multiple Outputs One advantage that the flyback topology offers is that additional output voltages can be obtained simply by adding windings. Designing a transformer for such a situation is beyond the scope of this document. For multiple windings, realize that the flyback winding signal is a combination of activity on all the secondary windings. Thus load regulation is affected by each windings load. Take care to minimize cross regulation effects.
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Setting Feedback Resistive Divider The expression for VOUT developed in the Operation section is rearranged to yield the following expression for the feedback resistors: R1= R2 VOUT +ISEC * ESR + RDS(ON) VFB * NSF above nominal so IPK = 3.64A . If there is a 10% tolerance on RSENSE and minimum VSENSE = 80mV, then RSENSE * 110% = 80mV/3.64A and nominal RSENSE = 20m. Round to the nearest available lower value. Selecting the Load Compensation Resistor -1 The expression for RCMP was derived in the Operation section as: RCMP = K1 * RSENSE * (1 - DC) * R1 * NSF = RS(OUT) ESR + RDS(ON)
(
)
Continuing the example, if ESR + RDS(ON) = 8m, R2 = 3.32k, then: R1= 3.4k choose 37.4k. It is recommended that the Thevenin impedance of the resistive divider (R1||R2) is roughly 3k for bias current cancellation and other reasons. Current Sense Resistor Considerations The external current sense resistor is used to control peak primary switch current, which controls a number of key converter characteristics including maximum power and external component ratings. Use a noninductive current sense resistor (no wire-wound resistors). Mounting the resistor directly above an unbroken ground plane connected with wide and short traces keeps stray resistance and inductance low. The dual sense pins allow for a fully Kelvined connection. Make sure that SENSE+ and SENSE- are isolated and connect close to the sense resistor to preserve this. Peak current occurs at 98mV of sense voltage VSENSE. So the nominal sense resistor is VSENSE/IPK. For example, a peak switch current of 10A requires a nominal sense resistor of 0.010. Note that the instantaneous peak power in the sense resistor is 1W, and that it is rated accordingly. The use of parallel resistors can help achieve low resistance, low parasitic inductance and increased power capability. Size RSENSE using worst-case conditions, minimum LP , VSENSE and maximum VIN. Continuing the example, let us assume that our worst-case conditions yield an IPK 40% 5 + 8 * 0.008 - 1 = 37.6k 1.232 * 1/ 3
Continuing the example: K1= VOUT 5 = = 0.116 VIN * Eff 48 * 90% 20m * (1- 0.455) 8m
If ESR + RDS(ON) = 8m RCMP = 0.116 * = 1.96k This value for RCMP is a good starting point, but empirical methods are required for producing the best results. This is because several of the required input variables are difficult to estimate precisely. For instance, the ESR term above includes that of the transformer secondary, but its effective ESR value depends on high frequency behavior, not simply DC winding resistance. Similarly, K1 appears as a simple ratio of VIN to VOUT times (differential) efficiency, but theoretically estimating efficiency is not a simple calculation. The suggested empirical method is as follows: 1. Build a prototype of the desired supply including the actual secondary components. 2. Temporarily ground the CCMP pin to disable the load compensation function. Measure output voltage while sweeping output current over the expected range. Approximate the voltage variation as a straight line, VOUT/IOUT = RS(OUT). 3. Calculate a value for the K1 constant based on VIN, VOUT and the measured efficiency.
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4. Compute: RCMP = K1 * RSENSE * R1 * NSF RS(OUT)
fOSC (kHz) 300 200
5. Verify this result by connecting a resistor of this value from the RCMP pin to ground. 6. Disconnect the ground short to CCMP and connect a 0.1F filter capacitor to ground. Measure the output impedance RS(OUT) = VOUT/IOUT with the new compensation in place. RS(OUT) should have decreased significantly. Fine tuning is accomplished experimentally by slightly altering RCMP . A revised estimate for RCMP is: RCMP = RCMP * 1+ RS(OUT)CMP RS(OUT)
100
50 30 100 COSC (pF) 200
3825 F02
Figure 2. fOSC vs OSC Capacitor Values
occur with slope compensation and system stability. Keep the sync pulse width greater than 500ns. Selecting Timing Resistors
where RCMP is the new value for the load compensation resistor, RS(OUT)CMP is the output impedance with RCMP in place and RS(OUT) is the output impedance with no load compensation (from step 2). Setting Frequency The switching frequency of the LT3825 is set by an external capacitor connected between the OSC pin and ground. Recommended values are between 200pF and 33pF yielding switching frequencies between 50kHz and , 250kHz. Figure 2 shows the nominal relationship between external capacitance and switching frequency. Place the capacitor as close as possible to the IC and minimize OSC trace length and area to minimize stray capacitance and potential noise pickup. You can synchronize the oscillator frequency to an external frequency. This is done with a signal on the SYNC pin. Set the LT3825 frequency 10% slower than the desired external frequency using the OSC pin capacitor, then use a pulse on the SYNC pin of amplitude greater than 2V and with the desired frequency. The rising edge of the SYNC signal initiates an OSC capacitor discharge forcing primary MOSFET off (PG voltage goes low). If the oscillator frequency is much different from the sync frequency, problems may
There are three internal "one-shot" times that are programmed by external application resistors: minimum on time, enable delay time and primary MOSFET turn-on delay. These are all part of the isolated flyback control technique, and their functions are previously outlined in the Theory of Operation section. The following information should help in selecting and/or optimizing these timing values. Minimum On Time (tON(MIN)) Minimum on time is the programmable period during which current limit is blanked (ignored) after the turn on of the primary side switch. This improves regulator performance by eliminating false tripping on the leading edge spike in the switch, especially at light loads. This spike is due to both the gate/source charging current and the discharge of drain capacitance. The isolated flyback sensing requires a pulse to sense the output. Minimum on time ensures that there is always a signal to close the loop. The LT3825 does not employ cycle skipping at light loads. Therefore, minimum on time along with synchronous rectification sets the switch over to forced continuous mode operation.
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The tON(MIN) resistor is set with the following equation: RtON(MIN) (k) = tON(MIN)(ns) - 104 1.063 overlap between the primary side switch and secondary side synchronous switch(es) and the subsequent current spike in the transformer. This spike will cause additional component stress and a loss in regulator efficiency. The primary gate delay resistor is set with the following equation: RPGDLY (k) = tPGDLY (ns) + 47 9.01
Keep RtON(MIN) greater than 70k. A good starting value is 160k. Enable Delay Time (ENDLY) Enable delay time provides a programmable delay between turn-off of the primary gate drive node and the subsequent enabling of the feedback amplifier. As discussed earlier, this delay allows the feedback amplifier to ignore the leakage inductance voltage spike on the primary side. The worst-case leakage spike pulse width is at maximum load conditions. So set the enable delay time at these conditions. While the typical applications for this part use forced continuous operation, it is conceivable that a secondaryside controller might cause discontinuous operation at light loads. Under such conditions the amount of energy stored in the transformer is small. The flyback waveform becomes "lazy" and some time elapses before it indicates the actual secondary output voltage. The enable delay time should be made long enough to ignore the "irrelevant" portion of the flyback waveform at light load. Even though the LT3825 has a robust gate drive, the gate transition time slows with very large MOSFETs. Increase delay time as required when using such MOSFETs. The enable delay resistor is set with the following equation: RENDLY (k) = tENDLY (ns) - 30 2.616
A good starting point is 27k. Soft-Start Functions The LT3825 contains an optional soft-start function that is enabled by connecting an external capacitor between the SFST pin and ground. Internal circuitry prevents the control voltage at the VC pin from exceeding that on the SFST pin. There is an initial pull-up circuit to quickly bring the SFST voltage to approximately 0.8V. From there it charges to approximately 2.8V with a 20A current source. The SFST node is discharged to 0.8V when a fault occurs. A fault is VCC too low (undervoltage lockout), current sense voltage greater than 200mV or the IC's thermal (over temperature) shutdown is tripped. When SFST discharges, the VC node voltage is also pulled low to below the minimum current voltage. Once discharged and the fault removed, the SFST recharges up again. In this manner, switch currents are reduced and the stresses in the converter are reduced during fault conditions. The time it takes to fully charge soft-start is: t SS = CSFST * 1.4V = 70ms * CSFST (F) 20A
Keep RENDLY greater than 40k. A good starting point is 56k. Primary Gate Delay Time (PGDLY) Primary gate delay is the programmable time from the turn-off of the synchronous MOSFET to the turn-on of the primary side MOSFET. Correct setting eliminates
UVLO Pin Function The UVLO pin provides a user programming undervoltage lockout. This is typically used to provide undervoltage lockout based on VIN. The gate drivers are disabled when UVLO is below the 1.24V UVLO threshold. An external resistive divider between the input supply and ground is used to set the turn-on voltage.
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The bias current on this pin depends on the pin voltage and UVLO state. The change provides the user with adjustable UVLO hysteresis. When the pin rises above the UVLO threshold a small current is sourced out of the pin, increasing the voltage on the pin. As the pin voltage drops below this threshold, the current is stopped, further dropping the voltage on UVLO. In this manner, hysteresis is produced. Referring to Figure 3, the voltage hysteresis at VIN is equal to the change in bias current times RA. The design procedure is to select the desired VIN referred voltage hysteresis, VUVHYS. Then: RA = where: IUVLO = IUVLOL - IUVLOH is approximately 3.4A RB is then selected with the desired turn-on voltage: RB = RA VIN(ON) VUVLO -1 VUVHYS IUVLO Even with good board layout, board noise may cause problems with UVLO. You can filter the divider but keep large capacitance off the UVLO node because it will slow the hysteresis produced from the change in bias current. Figure 3c shows an alternate method of filtering by splitting the RA resistor with the capacitor. The split should put more of the resistance on the UVLO side. Converter Start-Up The standard topology for the LT3825 utilizes a third transformer winding on the primary side that provides both feedback information and local VCC power for the LT3825 (see Figure 4). This power "bootstrapping" improves converter efficiency but is not inherently self-starting. Start-up is affected with an external "trickle-charge" resistor and the LT3825's internal VCC undervoltage lockout circuit. The VCC undervoltage lockout has wide hysteresis to facilitate start-up. In operation, the "trickle charge" resistor RTR is connected to VIN and supplies a small current, typically on the order of 1mA to charge CTR. Initially the LT3825 is off and draws only its start-up current. When CTR reaches the VCC turn-on threshold voltage the LT3825 turns on abruptly and draws its normal supply current.
VIN RTR VIN CTR VCC LT3825 VIN IUVLO VIN RA RB UVLO LT3825 VIN RA2 RA RB UVLO LT3825 CUVLO RB
3825 F03
If we wanted a VIN-referred trip point of 36V, with 1.8V (5%) of hysteresis (on at 36V, off at 34.2V): RA = 1.8V = 529k, use 523k 3.4A RB = 523k = 18.5k, use 18.7k 36V - 1 1.23V
IUVLO RA1
* *
IVCC
+
*
PG
GND
VON THRESHOLD VVCC IVCC 0 VPG
3825 F04
UVLO
(3a) UV Turning ON
(3b) UV Turning OFF
(3c) UV Filtering
Figure 3
Figure 4. Typical Power Bootstrapping
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Switching action commences and the converter begins to deliver power to the output. Initially the output voltage is low and the flyback voltage is also low, so CTR supplies most of the LT3825 current (only a fraction comes from RTR.) VCC voltage continues to drop until after some time, typically tens of milliseconds, the output voltage approaches its desired value. The flyback winding then provides the LT3825 supply current and the VCC voltage stabilizes. If CTR is undersized, VCC reaches the VCC turn-off threshold before stabilization and the LT3825 turns off. The VCC node then begins to charge back up via RTR to the turnon threshold, where the part again turns on. Depending upon the circuit, this may result in either several on-off cycles before proper operation is reached, or permanent relaxation oscillation at the VCC node. RTR is selected to yield a worst-case minimum charging current greater than the maximum rated LT3825 start-up current, and a worst-case maximum charging current less than the minimum rated LT3825 supply current. RTR(MAX) < and RTR(MIN) > VIN(MAX) - VCC(ON _ MIN) ICC(MIN) VIN(MIN) - VCC(ON _ MAX) ICC(ST _ MAX) this case, use the LT3837 which is identical to the LT3825 except that it lacks the internal VCC undervoltage lockout function. It is designed to operate directly from supplies in the range of 4.5V to 19V. See the LT3837 data sheet for further information. The LT3825 has an internal clamp on VCC of approximately 19.5V. This provides some protection for the part in the event that the switcher is off (UVLO low) and the VCC node is pulled high. If RTR is sized correctly the part should never attain this clamp voltage. Control Loop Compensation Loop frequency compensation is performed by connecting a capacitor network from the output of the feedback amplifier (VC pin) to ground as shown in Figure 5. Because of the sampling behavior of the feedback amplifier, compensation is different from traditional current mode switcher controllers. Normally only CVC is required. RVC can be used to add a "zero" but the phase margin improvement traditionally offered by this extra resistor is usually already accomplished by the nonzero secondary circuit impedance. CVC2 can be used to add an additional high frequency pole and is usually sized at 0.1 times CVC.
VC 9 CVC2 RVC CVC
3825 F05
Make CTR large enough to avoid the relaxation oscillatory behavior described above. This is complicated to determine theoretically as it depends on the particulars of the secondary circuit and load behavior. Empirical testing is recommended. Note that the use of the optional soft-start function lengthens the power-up timing and requires a correspondingly larger value for CTR. If you have an available input voltage within the VCC range, the internal wide hysteresis range UVLO function becomes counterproductive. In such cases it is better to operate the LT3825 directly from the available supply. In
Figure 5. VC Compensation Network
In further contrast to traditional current mode switchers, VC pin ripple is generally not an issue with the LT3825. The dynamic nature of the clamped feedback amplifier forms an effective track/hold type response, whereby the VC voltage changes during the flyback pulse, but is then "held" during the subsequent "switch on" portion of the
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next cycle. This action naturally holds the VC voltage stable during the current comparator sense action (current mode switching). AN19 provides a method for empirically tweaking frequency compensation. Basically it involves introducing a load current step and monitoring the response. Slope Compensation This part incorporates current slope compensation. Slope compensation is required to ensure current loop stability when the DC is greater than 50%. In some switcher controllers, slope compensation reduces the maximum peak current at higher duty cycles. The LT3825 eliminates this problem by having circuitry that compensates for the slope compensation so that maximum current sense voltage is constant across all duty cycles. Minimum Load Considerations At light loads, the LT3825 derived regulator goes into forced continuous conduction mode. The primary side switch always turns on for a short time as set by the tON(MIN) resistor. If this produces more power than the load requires, power will flow back into the primary during the "off" period when the synchronization switch is on. This does not produce any inherently adverse problems, though light load efficiency is reduced. Maximum Load Considerations The current mode control uses the VC node voltage and amplified sense resistor voltage as inputs to the current comparator. When the amplified sense voltage exceeds the VC node voltage, the primary side switch is turned off. In normal use, the peak switch current increases while FB is below the internal reference. This continues until VC reaches its 2.56V clamp. At clamp, the primary side MOSFET will turn off at the rated 98mV VSENSE level. This repeats on the next cycle. It is possible for the peak primary switch currents as referred across RSENSE to exceed the max 98mV rating because of the minimum switch on time blanking. If the voltage on VSENSE exceeds 206mV after the minimum turn-on time, the SFST capacitor is discharged, causing the discharge of the VC capacitor. This then reduces the peak current on the next cycle and will reduce overall stress in the primary switch. Short-Circuit Conditions Loss of current limit is possible under certain conditions such as an output short circuit. If the duty cycle exhibited by the minimum on time is greater than the ratio of secondary winding voltage (referred-to-primary) divided by input voltage, then peak current is not controlled at the nominal value. It ratchets up cycle-by-cycle to some higher level. Expressed mathematically, the requirement to maintain short-circuit control is: DCMIN = tON(MIN) * fOSC < where: tON(MIN) = primary side switch minimum on time ISC = short-circuit output current NSP = secondary-to-primary turns ratio (NSEC/NPRI) Other variables as previously defined Trouble is typically encountered only in applications with a relatively high product of input voltage times secondaryto-primary turns ratio and/or a relatively long minimum switch on time. Additionally, several real world effects such as transformer leakage inductance, AC winding losses, and output switch voltage drop combine to make this simple theoretical calculation a conservative estimate. Prudent design evaluates the switcher for short-circuit protection and adds any additional circuitry to prevent destruction. ISC * RSEC + RDS(ON) VIN * NSP
(
)
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Output Voltage Error Sources The LT3825's feedback sensing introduces additional sources of errors. The following is a summary list. The internal bandgap voltage reference sets the reference voltage for the feedback amplifier. The specifications detail its variation. The external feedback resistive divider ratio proportional directly affects regulated voltage. Use 1% components. Leakage inductance on the transformer secondary reduces the effective secondary-to-feedback winding turns ratio (NS/NF) from its ideal value. This increases the output voltage target by a similar percentage. Since secondary leakage inductance is constant from part to part (with a tolerance) adjust the feedback resistor ratio to compensate. The transformer secondary current flows through the impedances of the winding resistance, synchronous MOSFET RDS(ON) and output capacitor ESR. The DC equivalent current for these errors is higher than the load current because conduction occurs only during the converter's "off" time. So divide the load current by (1 - DC). If the output load current is relatively constant, the feedback resistive divider is used to compensate for these losses. Otherwise, use the LT3825 load compensation circuitry (see Load Compensation). If multiple output windings are used, the flyback winding will have a signal that represents an amalgamation of all these windings impedances. Take care that you examine worstcase loading conditions when tweaking the voltages. Power MOSFET Selection The power MOSFETs are selected primarily on the criteria of "on" resistance RDS(ON), input capacitance, drain-tosource breakdown voltage (BVDSS), maximum gate voltage (VGS) and maximum drain current (ID(MAX)). For the primary-side power MOSFET, the peak current is: IPK(PRI) = PIN X * 1+ MIN VIN(MIN) * DCMAX 2
where XMIN is peak-to-peak current ratio as defined earlier. For each secondary-side power MOSFET, the peak current is: IPK(SEC) = IOUT X * 1+ MIN 1- DCMAX 2
Select a primary-side power MOSFET with a BVDSS greater than: BVDSS IPK V LLKG + VIN(MAX) + OUT(MAX) CP NSP
where NSP reflects the turns ratio of that secondary-to-primary winding. LLKG is the primary-side leakage inductance and CP is the primary-side capacitance (mostly from the COSS of the primary-side power MOSFET). A snubber may be added to reduce the leakage inductance as discussed earlier. For each secondary-side power MOSFET, the BVDSS should be greater than: BVDSS VOUT + VIN(MAX) * NSP Choose the primary side MOSFET RDS(ON) at the nominal gate drive voltage (7.5V). The secondary side MOSFET gate drive voltage depends on the gate drive method. Primary side power MOSFET RMS current is given by: IRMS(PRI) = PIN VIN(MIN) DCMAX
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For each secondary-side power MOSFET RMS current is given by: IRMS(SEC) = IOUT 1 - DCMAX where: RDR is the gate driver resistance (10) VTH is the MOSFET gate threshold voltage fOSC is the operating frequency VGATE(MAX) = 7.5V for this part (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve. If you don't have a curve, use = 0.005/C * T for low voltage MOSFETs. The secondary-side power MOSFETs typically operate at substantially lower VDS, so you can neglect transition losses. The dissipation is calculated using: PD(SEC) = IRMS(SEC)2 * RDS(ON)(1 + )
b
3825 F06
Calculate MOSFET power dissipation next. Because the primary-side power MOSFET operates at high VDS, a transition power loss term is included for accuracy. CMILLER is the most critical parameter in determining the transition loss, but is not directly specified on the data sheets. CMILLER is calculated from the gate charge curve included on most MOSFET data sheets (Figure 6).
MILLER EFFECT a
VGS
QA QB GATE CHARGE (QG)
With power dissipation known, the MOSFETs' junction temperatures are obtained from the equation: TJ = TA + PD * JA where TA is the ambient temperature and JA is the MOSFET junction to ambient thermal resistance. Once you have TJ, iterate your calculations recomputing and power dissipations until convergence. Gate Drive Node Consideration The PG and SG gate drivers are strong drives to minimize gate drive rise and fall times. This improves efficiency but the high frequency components of these signals can cause problems. Keep the traces short and wide to reduce parasitic inductance. The parasitic inductance creates an LC tank with the MOSFET gate capacitance. In less than ideal layouts, a series resistance of 5 or more may help to dampen the ringing at the expense of slightly slower rise and fall times and efficiency. The LT3825 gate drives will clamp the max gate voltage to roughly 7.5V, so you can safely use MOSFETs with max VGS of 10V or larger.
Figure 6. Gate Charge Curve
The flat portion of the curve is the result of the Miller (gate-to-drain) capacitance as the drain voltage drops. The Miller capacitance is computed as: CMILLER = QB - Q A VDS
The curve is done for a given VDS. The Miller capacitance for different VDS voltages are estimated by multiplying the computed CMILLER by the ratio of the application VDS to the curve specified VDS. With CMILLER determined, calculate the primary-side power MOSFET power dissipation: PDPRI = IRMS(PRI)2 * RDS(ON) (1+ ) + VIN(MAX) * PIN(MAX) DCMIN * RDR * CMILLER * fOSC VGATE(MAX) - VTH
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Synchronous Gate Drive There are several different ways to drive the synchronous gate MOSFET. Full converter isolation requires the synchronous gate drive to be isolated. This is usually accomplished by way of a pulse transformer. Usually the pulse driver is used to drive a buffer on the secondary as shown in the application on the front page of this data sheet. However, other schemes are possible. There are gate drivers and secondary side synchronous controllers available that provide the buffer function as well as additional features. Capacitor Selection In a flyback converter, the input and output current flows in pulses, placing severe demands on the input and output filter capacitors. The input and output filter capacitors are selected based on RMS current ratings and ripple voltage. Select an input capacitor with a ripple current rating greater than: IRMS = PIN VIN(MIN) 1 - DCMAX DCMAX IRMS = 8 A Keep input capacitor series resistance (ESR) and inductance (ESL) small, as they affect electromagnetic interference suppression. In some instances, high ESR can also produce stability problems because flyback converters exhibit a negative input resistance characteristic. Refer to Application Note 19 for more information. The output capacitor is sized to handle the ripple current and to ensure acceptable output voltage ripple. The output capacitor should have an RMS current rating greater than: IRMS = IOUT DCMAX 1- DCMAX 52.6% = 8.43A 1 - 52.6%
Continuing the example: :
This is calculated for each output in a multiple winding application. ESR and ESL along with bulk capacitance directly affect the output voltage ripple. The waveforms for a typical flyback converter are illustrated in Figure 7. The maximum acceptable ripple voltage (expressed as a percentage of the output voltage) is used to establish a starting point for the capacitor values. For the purpose of simplicity we will choose 2% for the maximum output ripple, divided equally between the ESR step and the
Continuing the example: IRMS = 44 . 4W 1 - 52 . 6 % = 1 . 17 A 36 V 52 . 6 %
PRIMARY CURRENT
IPRI
SECONDARY CURRENT
IPRI N
VCOUT OUTPUT VOLTAGE RIPPLE WAVEFORM
RINGING DUE TO ESL VESR
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Figure 7. Typical Flyback Converter Waveforms
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LT3825 APPLICATIONS INFORMATION
charging/discharging V. This percentage ripple changes, depending on the requirements of the application. You can modify the equations below. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor is determined by: ESRCOUT 1% * VOUT * (1- DCMAX ) IOUT The design of the filter is beyond the scope of this data sheet. However, as a starting point, use these general guide lines. Start with a COUT 1/4 the size of the nonfilter solution. Make C1 1/4 of COUT to make the second filter pole independent of COUT . C1 may be best implemented with multiple ceramic capacitors. Make L1 smaller than the output inductance of the transformer. In general, a 0.1H filter inductor is sufficient. Add a small ceramic capacitor (COUT2) for high frequency noise on VOUT. For those interested in more details refer to "Second-Stage LC Filter Design," Ridley, Switching Power Magazine, July 2000, p8-10. Circuit simulation is a way to optimize output capacitance and filters, just make sure to include the component parasitics. LTC SwitcherCADTM is a terrific free circuit simulation tool that is available at www.linear.com. Final optimization of output ripple must be done on a dedicated PC board. Parasitic inductance due to poor layout can significantly impact ripple. Refer to the PC Board Layout section for more details. IC Thermal Considerations Take care to ensure that the LT3825 junction temperature does not exceed 125C. Power is computed from the average supply current, the sum of quiescent supply current (ICC in the specifications) plus gate drive currents. The primary gate drive current is computed as: fOSC * QG where QG is the total gate charge at max VGS (obtained from the gate charge curve) and f is the switching frequency. Since the synchronous driver is usually driving a capacitive load, the synchronous gate drive power dissipation is: fOSC * CS * VSGMAX where CS is the SG capacitive load and VSGMAX is the SG pin max voltage.
RLOAD SwitcherCAD is a trademark of Linear Technology Corporation.
The other 1% is due to the bulk C component, so use: COUT IOUT 1% * VOUT * fOSC
In many applications the output capacitor is created from multiple capacitors to achieve desired voltage ripple, reliability and cost goals. For example, a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic capacitor satisfies the required bulk C. Continuing our example, the output capacitor needs: ESRCOUT 1% * COUT 5V * (1- 49%) 8A = 3m
8A = 800F 1% * 5 * 200kHz
These electrical characteristics require paralleling several low ESR capacitors possibly of mixed type. Most capacitor ripple current ratings are based on 2000 hour life. This makes it advisable to derate the capacitor or to choose a capacitor rated at a higher temperature than required. One way to reduce cost and improve output ripple is to use a simple LC filter. Figure 8 shows an example of the filter.
L1 0.1H FROM SECONDARY WINDING C1 47F 3 COUT 470F VOUT COUT2 1F
3825 F08
Figure 8
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25
LT3825 APPLICATIONS INFORMATION
The total IC dissipation is computed as: PD(TOTAL) = VCC * (ICC + fOSC * (QGPRI + CS * VSGMAX)) VCC is the worst-case LT3825 supply voltage. Junction temperature is computed as: TJ = TA + PD * JA where: TA is the ambient temperature JA is the FE16 package junction-to-ambient thermal impedance (40C/W). PC Board Layout Considerations In order to minimize switching noise and improve output load regulation, connect the GND pin of the LT3825 directly to the ground terminal of the VCC decoupling capacitor, the bottom terminal of the current sense resistor, the ground terminal of the input capacitor, and the ground plane (multiple vias). Place the VCC capacitor immediately adjacent to the VCC and GND pins on the IC package. This capacitor carries high di/dt MOSFET gate drive currents. Use a low ESR ceramic capacitor. Take care in PCB layout to keep the traces that conduct high switching currents short, wide and with minimal overall loop area. These are typically the traces associated with the switches. This reduces the parasitic inductance and also minimizes magnetic field radiation. Figure 9 outlines the critical paths. Keep electric field radiation low by minimizing the length and area of traces (keep stray capacitances low). The drain of the primary side MOSFET is the worst offender in this category. Always use a ground plane under the switcher circuitry to prevent coupling between PCB planes. Check that the maximum BVDSS ratings of the MOSFETs are not exceeded due to inductive ringing. This is done by viewing the MOSFET node voltages with an oscilloscope. If it is breaking down either choose a higher voltage device, add a snubber or specify an avalanche-rated MOSFET.
T1
VCC CVCC LT3825 VCC PG GND MP GATE TURN-OFF RSENSE VCC LT3825 VCC SG T2 CR GATE TURN-ON
VIN
* * *
CVIN
OUT
COUT Q4 GATE TURN-ON MS Q3 GATE TURN-OFF
*
GND
*
3825 F09
Figure 9. High Current Paths
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26
LT3825 APPLICATIONS INFORMATION
Place the small-signal components away from high frequency switching nodes. This allows the use of a pseudo-Kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the IC ground pin in one direction (to the bottom plate of the VCC decoupling capacitor) and small-signal currents flow in the other direction. Keep the trace from the feedback divider tap to the FB pin short to preclude inadvertent pickup. For applications with multiple switching power converters connected to the same input supply, make sure that the input filter capacitor for the LT3825 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple and this could interfere with the LT3825 operation. A few inches of PC trace or wire (L 100nH) between the CIN of the LT3825 and the actual source VIN is sufficient to prevent current sharing problems.
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27
LT3825 TYPICAL APPLICATIONS
48V to 5V at 8A Isolated Supply
4 T1
*
5 VIN+ 36V TO 72V 1 P6SMB100A MBRS1100 3
7 8 9
+
2.2F 100V BAS21 402k 1% 29.4k 1% R7 20 SG VCC FB UVLO 15k 1% 3.01k 1% LT3825 SENSE- VC OSC GND SFST CCMP 0.22F 0.1F 100k 10nF 680pF PG SG SENSE+ 47k 1/4W
* *
10 11 12
470F 6TPE470MI x4
0.1F 2.2nF 250V
VOUT+ 5V 8A
+
47F 20V
0.1F
Si4490DY
1nF 10 1/4W SG 0.03 1W 330 0.1F 8 PA0184 1
Si7336ADP x2
B0540W 47
FMMT718 FMMT618 1F 2.2nF 15
PGDLY tON SYNC RCMP ENDLY 12k 100k 2.1k 1% 100k 47pF
*
*5
BAT54 4
3825 TA02a
10k
ALL CAPACITORS 25V UNLESS OTHERWISE NOTED T1: EDFD25-3F3 GAP FOR LP = 200H (i.e., AL = 200nH/T2) PINS 1 TO 3, 32T OF 2 x 32AWG PINS 4 TO 5, 11T OF 1 x 32AWG PINS 1 TO 3, 32T OF 2 x 32AWG PINS 10, 11, 12 TO PINS 7, 8, 9, 4T OF 5 MIL COPPER FOIL PINS 1 TO 3, 32T OF 2 x 32AWG 2 MIL POLYESTER FILM
Efficiency vs Load Current
94 92 90 EFFICIENCY (%) OUTPUT (V) 88 86 84 82 80 78 1 2 3 6 5 4 LOAD CURRENT (A) 7 8 48VIN 72VIN 36VIN 5.25 5.20 5.15 5.10 5.05 5.00 4.95 4.90 4.85 4.80 4.75
Output Regulation vs Load Current
48VIN 36VIN 72VIN
1
2
5 4 3 6 LOAD CURRENT (A)
7
8
3825 TA02b
3825 TA02c
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28
LT3825 TYPICAL APPLICATIONS
48V to 3.3V at 6A Isolated Supply
T1 PULSE PB2134 4 7
*
5 VIN+ 36V TO 72V 1
8 9
+
0.82F 100V BAS21 402k 1% 26.1k 1% R7 20 SG VCC FB UVLO 15k 1% 3.01k 1% PGDLY tON SYNC RCMP 15k 100k LT3825 SENSE- VC ENDLY 62k 47pF OSC GND SFST CCMP 0.22F 0.1F 10k 3.3nF 680pF PG SG SENSE+ 47k 1/4W
* *
10 11 12
150F 6TPB150ML x3
0.1F 2.2nF 250V
VOUT+ 3.3V 6A
+
47F 20V
3 0.1F
B0540W Si4490DY
47 1F
FMMT618 Si7892DP FMMT718 SG 0.04 1W 330 0.1F 8 PA0184 1 4
3825 TA03a
2.2nF
15
866 1%
*
*
5 BAT54 10k
Efficiency vs Load Current
90 36VIN 88 EFFICIENCY (%) 72VIN 48VIN 3.38 3.33 OUTPUT (V) 3.43
Output Regulation vs Load Current
86
36VIN 3.28 72VIN 3.23 48VIN
84
82
3.18 3.13 1 2 4 3 LOAD CURRENT (A) 5 6
3825 TA03b
80
1
2
3
4
5
6
3825 TA03c
LOAD CURRENT (A)
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29
LT3825 TYPICAL APPLICATIONS
48V to 5V at 12A Isolated Supply
L1 0.1H T1 28.7k 1% 3.01k 1% 402k 1% 2.2F 100V UVLO 15k 1% LT3825 PGDLY tON SYNC RCMP ENDLY 12k 100k 750 150k 47pF SENSE- VC CCMP 0.01F 0.1F FB BAS21 T1 100pF 250V 47k 1/4W 20
VIN 36V TO 72V
+
* *
C1 TO C4 47F x3 B0540W 47 Q1
C5 470F
VOUT+ 3.3V 12A 2.2F 250V
*
20
+
47F VCC SG SG PG
Si4490DY SENSE+ 0.02 1/2W Si7336ADP Q2 SG 1F 330 0.1F 10nF 10k 1nF
3825 TA04a
15 2.2nF
OSC GND SFST
*
PA0184
*
10k BAT54
C1 TO C4: TDK C3225X5R0J476M C5: SANYO 6TPD470M L1: VISHAY IHLP2525CZERR10M
Q1: ZETEX FMMT618 Q2: ZETEX FMMT718 T1: PULSE PA1477NL
Efficiency vs Load Current
92 90 36VIN 88 EFFICIENCY (%) OUTPUT (V) 48VIN 86 72VIN 84 82 80 78 2 3 4 9 5 678 LOAD CURRENT (A) 3.33 3.28 3.43 3.38
Output Regulation vs Load Current
36VIN 48VIN 72VIN
3.23 3.18 3.13 2 4 6 8 LOAD CURRENT (A) 10 12
3825 TA04c
10 11 12
3825 TA04b
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30
LT3825 PACKAGE DESCRIPTION
FE Package 16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
4.90 - 5.10* (.193 - .201) 3.58 (.141) 16 1514 13 12 1110 9
3.58 (.141)
6.60 0.10 4.50 0.10
SEE NOTE 4
2.94 (.116) 0.45 0.05 1.05 0.10 0.65 BSC
6.40 2.94 (.252) (.116) BSC
RECOMMENDED SOLDER PAD LAYOUT
12345678 1.10 (.0433) MAX
0 - 8
4.30 - 4.50* (.169 - .177)
0.25 REF
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE
0.195 - 0.30 (.0077 - .0118) TYP
0.05 - 0.15 (.002 - .006)
FE16 (BC) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LT3825 RELATED PARTS
PART NUMBER LT1424-5 LT1424-9 LT1425 LTC1698 LT1725 LT1737 LTC1871 LTC3710 LT3781/LT1698 LTC3803 LTC3806 DESCRIPTION Isolated Flyback Switching Regulator Isolated Flyback Switching Regulator Isolated Flyback Switching Regulator Isolated Secondary Synchronous Rectifier Controller General Purpose High Power Isolated Flyback Controller High Power Isolated Flyback Controller Wide Input Range Current Mode No RSENSETM Controller Secondary Side Synchronous Post Regulator 36V to 72V Input Isolated DC/DC Converter Chipset SOT-23 Flyback Controller Synchronous Flyback DC/DC Controller COMMENTS 5V Output Voltage, No Optoisolator Required 9V Output Voltage, Regulation Maintained Under Light Loads No Third Winding or Optoisolator Required Isolated Power Supplies, Contains Voltage Merging, Optocoupler Driver, Primary Synchronization Circuit Suitable for Telecom or Offline Input Voltage Powered from a DC Supply Voltage 50kHz to 1MHz, Boost, Flyback and SEPIC Topology Generates a Regulated Auxiliary Output in Isolated DC/DC Converters. Dual N-Channel MOSFET Synchronous Drivers Synchronous Operation: Overvoltage/Undervoltage Protection, 10W to 100W Power Supply, 1/2 to 1/4 Brick Footprint Adjustable Slope Compensation, Internal Soft-Start, 200kHz Medium Power Multiple Outputs, 250kHz Soft-Start
No RSENSE is a trademark of Linear Technology Corporation.
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32 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0108 REV A * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2007

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